
Chang Yong Kang
Develop silicon architectures for number crunching (signal processing), flow control (protocol implementation), and integration (SoC), in highly multi-disciplinary... | Cupertino, California, United States
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Chang Yong Kang’s Emails cy****@al****.utexas
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Chang Yong Kang’s Location Cupertino, California, United States
Chang Yong Kang’s Expertise Develop silicon architectures for number crunching (signal processing), flow control (protocol implementation), and integration (SoC), in highly multi-disciplinary (marketing, platform, HW, SW, etc.) project environment. Fully capable of hands-on execution and experienced in design team building and leading. Pragmatic yet standalone-research-capable for advanced topics. Specialties: Firm theoretical background in DSP (including communications), computer arithmetic, and computer architecture, as applied to designing specialty microprocessors (VLIW and vector processors) and application-specific HW accelerators for wireless communications, digital media, cryptography, and sensing. Fluency in SoC architecture, especially in SoC backbone building; in-depth understanding of Network-on-Chip (NoC) theories and practices for streaming applications, as well as conventional SoC bus protocols such as AHB, OCP, and IOSF (Intel-proprietary). Knowledgeable in such topics as producer-consumer model, PCI ordering, deadlock/starvation prevention, multi-level arbitration, and SoC security. Well versed in the Intel chipset architecture context. Full grasp of standard-cell based design flow from RTL to APR. Engineering management skills to provide leadership for large-scale projects.
Chang Yong Kang’s Current Industry Apple
Chang
Yong Kang’s Prior Industry
Samsung Electronics
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Cirrus Logic
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Alereon
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Intel
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Apple
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Work Experience

Apple
Touch ASIC Architect
Sun Jul 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Silicon Architect
Wed Mar 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jun 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Alereon
Senior Design Engineer
Sun May 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Mar 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Cirrus Logic
Lead Design Engineer
Mon May 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun May 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)
Samsung Electronics
Senior Design Engineer
Wed Sep 01 1993 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat May 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time)